Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and other types of logic blocks, such as memories, microprocessors, digital signal processors (DSPs), and the like. The CLBs, IOBs, and other logic blocks are interconnected by a programmable interconnect structure. The CLBs, IOBs, logic blocks, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, logic blocks, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as digital clock managers (DCMs), input/output (I/O) transceivers, boundary scan logic, and the like.
As semiconductor technology has advanced, the amount and speed of logic available on an IC, such as an FPGA, has increased more rapidly than the number and performance of I/O connections. As a result, IC die stacking techniques have received renewed interest to address the interconnection bottleneck of high-performance systems. In stacked IC applications, two or more ICs are stacked vertically and interconnections are made between them.
One process for forming stacked-die integrated circuit devices, typically referred as a “via last” process forms through die vias after device and metal layers have been formed on the face side of the die. Metal layers are typically implemented in alternating layers of vertical and horizontal wiring tracks. More particularly, one layer will include only horizontal wiring tracks and the next layer will include only vertical wiring tracks. Wiring segments that extend within horizontal and vertical wiring tracks electrically connect with overlying and underlying structures using contacts and vias.
In the via-last process an additional metal layer is formed over the through die vias. This additional metal layer connects the through die vias to the wiring segments in the horizontal and vertical wiring tracks of underlying metal layers. The backside of the die is ground to expose the through die vias and contacts are formed on the backside of the first die that connect to the through die vias. The second die is then attached to the backside of the die, with the contacts electrically coupling the circuitry of the first die to the circuitry of the second die.
When a via-last fabrication process is used to form a FPGA die, because FPGA devices typically include columns of tiles that have uniform characteristics, it can be difficult to design the wiring of the layers that include horizontal and vertical wiring tracks. For example, if a column of tiles includes through die vias, since all of the wiring layers that include horizontal wiring tracks are interrupted by the through die vias, there may not be a sufficient number of uninterrupted wiring tracks to provide the needed connectivity. Accordingly, there exists a need in the art for a method and apparatus that will allow for increased connectivity across wiring tracks that are interrupted by through die vias.